1. Field of the Invention
The present invention relates to an image processing apparatus. More particularly, the present invention relates to an image processing apparatus including a high-speed serial bus and a method of transmitting a reference clock via the high-speed serial bus.
2. Description of the Related Art
Peripheral component interconnect express (registered trademark) (hereinafter, “PCI Express”) is a type of high-speed serial buses. A high-speed bus is an interface capable of transmitting and receiving data at a high speed (about 100 Mbps or higher) through a single transmission path by use of serial transmission technique. The PCI Express, a successive version of PCI standards, is a standard expansion bus generally used in computers. The PCI Express is featured by transmission by using low-voltage differential signals, point-to-point full-duplex communication lines (capable of simultaneous transmit and receive), packetized split transaction, and improved scalability capable of establishing communication between different link structures.
Given below are examples of conventional technologies that relate to the PCI Express. Japanese Patent Application Laid-Open No. 2005-321921 discloses a serial-data transmitter, an image outputting device, an image inputting device, and an image processing apparatus that implement a low-cost and low-power consumption interface in an image device that can perform a high-speed serial data communication specifically based on PCI Express standards. Japanese Patent Application Laid-Open No. 2005-151448 discloses a data-transmission system, an image forming system, and a data-transmission program that provide improved data-transfer efficiency by avoiding transfer-path competition that can happen in parallel processing of a plurality of independent data transfers.
In the above-described conventional devices that includes the interface based on the PCI Express standards, when a spread-spectrum reference clock is input in a state that a voltage output from a power source of a device that receives the reference clock to the PCI Express input/output (I/O) interface is lower than a predetermined operating-voltage, the receiver device may go out of order.